This section is intended to provide a background or context to the invention that is recited in the claims. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived, implemented or described. Therefore, unless otherwise indicated herein, what is described in this section is not prior art to the description and claims in this application and is not admitted to be prior art by inclusion in this section.
The following abbreviations that may be found in the specification and/or the drawing figures are defined as follows:    DDPS direct digital period synthesis    IQ in phase-quadrature    LFSR linear feedback shift register    LO local oscillator    LSB least significant bit(s)    TD-DDS time-domain direct digital synthesizer
Reference may be made to Dorin E. Calbaza, Yvon Savaria, “A Direct Digital Period Synthesis Circuit”, IEEE Journal of Solid-State Circuits, Vol. 37, No. 8, August 2002, pgs. 1039-1045). The Calbaza et al. article proposes a DDPS architecture that allows a circuit output frequency to be higher than a reference frequency. A delay modulator, which takes additional bits from a phase accumulator output, is used to reduce the timing jitter level and thus the magnitude of spurs in the output.
FIGS. 11A, 11B and 11C are circuit diagrams and a timing diagram of the direct digital period synthesis circuit proposed by Calbaza et al., and reproduce FIGS. 2, 3 and 4 of the Calbaza et al. publication.
As is stated in the Calbaza et al. publication, the DDPS can multiply a reference clock frequency with a fractional number. FIGS. 11A and 11B, respectively, present the general block diagram and the timing diagram of the DDPS circuit. Shown in FIG. 11A is a transition generator (TGen), which produces several output signals at the same frequency as the input reference clock (Clk), but with evenly distributed phases. A transition selector circuit (TSel) is responsible for selecting one of the transitions provided by the TGen. This transition is propagated to an output clock (Oc). Transition selection is done according to the output produced by a phase accumulator (Acc). The ability to select the transition that propagates to the output clock allows the DDPS to numerically control its output period. A conventional DLL-based frequency multiplier propagates transitions in their natural order and its output period is fixed.
The TGen circuit was implemented by using a differential ring oscillator composed of 32 differential buffers/inverters, connected as a ring oscillator. For instance, with a 3.2 ns ring oscillator period, the TGen can produce 64 derived copies of the clock with transitions delayed by 50 ps from each other. In this case, only the 6 most significant bits (MSBs) of the Acc output are used to select one of the 64 transitions. The propagated transition is also used to control the phase increment. To simplify the block diagram, the TSel was limited to four phases, Ck0 to Ck3, produced by the transition generator and selected according to the output of a 2-bit phase accumulator. Assuming a 3.2 ns period input clock, Ck0 to Ck3 are delayed from each other by 800 ps. By using Oc to control the phase Acc, its period can be made equal to a fraction of the Clk clock period (T), where the fraction is specified by the phase increment Ph.
The timing diagram of FIG. 11B presents the case for Ph=0.01b, which is the binary representation of ¼. In response to clock pulses driving the Acc clock, the output phase goes from 0.00b to 0.01b, 0.10b, 0.11b, and then the sequence repeats.
For example, assume that the circuit starts with an output phase equal to 0.00b. This selects Ck0 to be propagated at the output Oc. After a propagation delay that particular transition will generate a pulse on Oc. That pulse will trigger the update of the Acc content that will become 0.01b, thus the next output phase becomes 0.01b, which will select Ck1 for propagation to Oc. If the selected output phase changes sufficiently before the arrival of Ck1 the DDPS acts as a frequency multiplier. The pulses at the Acc clock input change its digital output value according to the sequence 0.10b, 0.11b, 0.00b, 0.01b, and so on, selecting Ck2, Ck3, Ck0, Ck1, to be propagated to the output clock Oc. For another input phase number Ph=0.11b the output phase would follow the sequence 0.00b, 0.11b, 0.10b, 0.01b and so on, giving an output period equal to three times the delay between Ck0 and Ck1.
The frequency of the output signal is given byfoc=fClk/Ph, where Ph<1 is the phase increment and fClk is the frequency of any Cki clock. Since Ph is less than 1, the output frequency is greater than the input clock frequency.
It is said by Calbaza et al. that a phase accumulator with a bit resolution larger than the number of bits required to address the inputs of the transition selector can express the output frequency with better precision. For instance, a 32-bit phase accumulator allows controlling the output clock frequency with sub-hertz precision. However, the time resolution of the output transitions and implicitly the output jitter, is determined by the time separation between the phases produced by the transition generator TGen.
The TSel selects one of the phases provided by TGen and propagates it to its output. Ideally, TSel propagates each phase with the same delay to avoid inducing jitter. Delay modulation can be included in the TSel circuit to improve the resolution of the DDPS. This reduces the theoretical jitter of the DDPS to a fraction of an inverter delay.
FIG. 11C is a block diagram of the TSel circuit. Again, to simplify the illustration, only the two MSBs of the phase accumulator output control the TSel circuit. The next two LSBs of the phase accumulator output are used to control the propagation delay through the output buffer. The circuit comprises a programmable logic array decoder (PLA decoder), four resettable D flip-flops, an OR gate, and a buffer with a controlled propagation time. The PLA decoder receives the 2 MSBs (PHMSB) of the phase accumulator and sets the D0-D3 lines according to the received code. The PLA was used for convenience, and it also occupies a small size, due to its regular layout structure, and produces a small delay since transistors are connected in parallel.
For instance, if PHMSB=0.1, D1 will be at 1. Thus, Ck1 is selected and when its rising edge arrives, the corresponding line becomes ‘1’. This ‘1’ propagates through the OR gate, resetting all of the D flip-flops and generating a pulse to the output clock Oc. The pulse on Oc activates the phase accumulator, selecting a new phase to be propagated, as discussed above.
It is said by Calbaza et al. that it is important to equalize the propagation delays from the selected Cki (i=0-3) to the output of the OR gate, since variations of this propagation delay cause jitter. Considering a 500 ps propagation delay, a 5% mismatch would produce about 25 ps period jitter.
It is also said by Calbaza et al. that the time resolution of TSel can be improved with a delay modulator that may be implemented with a buffer controlled by the 2 bits of the output phase of Acc (PHLSB) that directly follow the set of MSBs used to control the PLA decoder. These two bits are said to modulate the propagation delay through the buffer.
However, following the techniques disclosed by Calbaza et al. undesirable spurs in the output spectrum appear due to truncation of the phase accumulator output.
In “A Digital Frequency Synthesizer for Cognitive Radio Spectrum Sensing Applications”, Tapio Rapinoja, Kari Stadius, Liangge Xu, Saska Lindfors, Risto Kaunisto, Aarno Pärssinen and Jussi Ryynanen, IEEE Radio Frequency Integrated Circuits Symposium 2009, June 2009, pgs. 423-426, there is disclosed an enhancement to the DDDS, more specifically a TD-DDS architecture. Reference may also be made to commonly owned U.S. patent application Ser. No. 12/291,255, filed Nov. 6, 2008, “Frequency Synthesizer Having a Plurality of Independent Output Tones”, Saska Lindfors et al., incorporated by reference herein.